Accurately measuring time delay, or skew, between two or more clocks on an integrated circuit (IC) die has many practical applications. This capability can be used to characterize and adapt phase interpolator (PI) linearity, the lock error in a phase locked loop (PLL) or delay locked loop (DLL), the phase spacing in multi-phase clock generators such as a DLL or PLL, and skew between clock domains. In communications, PI characterization or adaptation can enable accurate on-die BER eye margining. Conventional techniques used to characterize different aspects of phase delay fail to produce (1) accuracy that is independent of variation and process, voltage, and temperature (PVT), combined with (2) a digitized measurement of phase delay that can be read off-chip or used on-chip to adapt or correct for the phase delay non-ideality.
One conventional technique uses external, i.e., off-die, equipment and external measurements. For example, PI and DLL/PLL phase spacing can be characterized by bringing clock signals off-die and into external equipment to characterize delays. This approach lacks repeatability and accuracy, increases test time, and requires bulky, expensive, external equipment, all of which make the approach unsuitable for either accurate or high volume delay measurements. Another technique uses an on-die delay line as a “golden” delay reference. The accuracy of this approach is limited by PVT effects on the delay line reference, and the timing resolution of practical circuits associated with the delay line. Other techniques require voltage-offset compensated comparators and regulated reference currents, which are analog in nature and also limited by PVT effects.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.